In memory chips, column multiplexor area is dominated by the area associated with a number of routing wires, instead of the device area. For example, in a 128 column decoding scheme with four reference columns, the column multiplexor height area is dominated by the number of routing wires of 264 column selection signals at a predefined upper level of a memory chip (i.e., bit line and source line signals). Therefore, to have a compact memory chip layout, a simplified column multiplexor decoding scheme is needed which does not affect the functionality of the column multiplexor decoding scheme.